This invention relates to a negative voltage detection circuit for generating a control signal which controls the level of a negative voltage generated in a chip by a charge pump or the like, or to a non-volatile semiconductor memory device incorporating the negative voltage detection circuit.
In a flash memory device in which programmed data is erased by applying a negative voltage to a gate thereof, a charge pump (a charge pump circuit) generates the erasing negative voltage within a range from -5 to -11 V in a chip. The negative voltage must be controlled with high precision in the erasing rate, the withstand voltage of the element, and the reliability in erasing.
FIG. 1 is a circuit diagram showing the general relationship between the charge pump and a negative voltage detection circuit. A negative voltage detection circuit 112 detects whether or not a negative voltage VBB as an output of a charge pump (C.P) 111 has a desired level, and then outputs a signal SVBB in accordance with the detection result: when the level of the negative voltage VBB is lower than the desired level, the control signal SVBB is generated to stop the charge pump, and in the other case, to operate the charge pump 1. As is clear from this, the circuit shown in FIG. 1 executes the feedback control of the charge pump 111 to set the negative voltage VBB output from the charge pump 111 at a desired level, thereby obtaining the desired level of the erasing negative voltage.
FIG. 2 is a circuit diagram showing the conventional negative voltage detection circuit such as shown in FIG. 1 by the reference numeral 112. In this conventional negative voltage detection circuit, a P-channel MOS transistor (PMOS) the gate of which is connected to ground has a current path located between a power source voltage VDD and an input node VG of an inverter IV. Between the node VG and a negative voltage source VBB, a plurality of N-channel MOS transistors (NMOS 1-n) are arranged to connect the current paths in series. Among the N-channel MOS transistors, a transistor NMOS 1 has a source connected to the node VG which is applied with a ground potential, and the other transistors NMOSs 2-n each has a gate connected to its own source.
The potential at the node VG in the circuit shown in FIG. 2 can be represented by the following formulas using the threshold voltage V.sub.th of the N-channel MOS transistors and the number of the transistors: EQU VG=VBB+(n-1).times.V.sub.th (when VBB+n.times.V.sub.th &lt;VDD)(2) EQU VG=VDD(when VBB+n.times.V.sub.th .gtoreq.VDD) (3)
The transistor NMOS 1 shown in FIG. 1 is turned ON when the negative voltage VBB increases (the level of the negative voltage becomes higher). When the transistor NMOS 1 is turned ON, the potential VDD is dropped at the node VG to exceed the threshold voltage of the inverter IV, and the level of the signal SVBB is inverted from low to high. In short, the formula (2) is satisfied in the region where the negative voltage VBB has a value to invert the signal SVBB. In other words, when the potential of the source of the transistor NMOS 1 is lower than -V.sub.th (the threshold voltage of the transistor NMOS 1), the transistor NMOS 1 is turned on, and the potential of the node VG is rapidly dropped.
The above-mentioned relationship, however, can be attained only by using the threshold voltage V.sub.th of a general MOS transistor, and may be affected by the variations in the manufacturing process or by the temperature dependency of the MOS transistor. The switching level of the transistor NMOS 1, i.e., the detection level of the negative voltage VBB is fluctuated by the influence of these factors. In addition, the detection level can be changed only by changing the number of the transistors, and thus detection with high precision cannot be attained.